1. Field of the Invention
The present invention relates to interface circuits for translating voltage levels of signals between circuits biased by unequal power supply voltages, and in particular, to such interface circuits with minimum power consumption during initial application of the power supply voltages.
2. Related Art
Referring to FIG. 1, a power supply detection circuit has become an essential part of the input/output (I/O) interface in digital and mixed signal integrated circuits, or “chips”, having multiple, e.g., two, power supplies. For example, a typical example of such a chip 10 includes, at a minimum, core circuitry 12 biased by a core power supply voltage VDD, and I/O interface circuitry 14 powered by another power supply voltage VDDIO. Typically, the core circuit 12 operates at a lower power supply voltage to minimize power consumption, while the I/O circuit 14 operates, at least in part, at a higher power supply voltage so as to provide appropriate signal levels to and receive higher level signals from circuitry outside the chip 10 which often operates at such higher power supply voltage. Additionally, the core circuit 12 is often primarily, if not exclusively, digital circuitry using insulated gate field effect transistors (IGFETs, often still referred to as metal oxide semiconductor field effect transistors, or MOSFETs) having thin gate oxides, while the I/O circuit 14 uses transistors having thicker gate oxides. Accordingly, the core power supply voltage VDD is less than the I/O power supply voltage VDDIO.
Depending upon the functions to be performed by the chip 10, various signals 15 are conveyed between the core 12 and I/O 14 circuits. Some signals 15a may flow exclusively from the core 12 to the I/O 14 circuit while other signals 15b may flow exclusively in the opposite direction. Additionally, some signals 15c may be bi-directional between the circuits 12, 14. Similarly, the I/O circuit 14 provides outgoing signals 11a and receives incoming signals 11b, and may also exchange bi-directional signals 11c. 
During initial application of the power supply voltages VDD, VDDIO, a power supply detection circuit monitors the actual reception of the voltages. In many instances, the I/O power supply voltage VDDIO is applied, or asserted, prior to application of the core power supply voltage VDD. This is done to establish the appropriate interfaces between the I/O circuit 14 and the core circuit 12. Moreover, there should be virtually no current consumption by the I/O driver output circuit. During this interval, however, the output interfaces, i.e., those electrodes responsible for providing communication between the chip 10 and other external circuits (not shown) must remain disabled. This is often problematic since the output enable signal is typically generated by the core circuit 12 which is powered by the core power supply voltage VDD, which has not yet been applied.
Accordingly, it is desirable to provide circuitry for detecting the core power supply voltage VDD while still disabling the output interfaces within the I/O circuit 14. More importantly, it would be desirable to provide this capability while consuming minimal, if any, power, consistent with the goals of low power consumption achieved during normal circuit operation due to the lower core power supply voltage VDD.